Let' beep! A Music Synthesizer with Cyclone V FPGA
This page describes the intended FPGA music synthesizer. It is a improved reproduction of my PLD synthesizer and mostly rebuilt. Currently the PCB Design is in progress.
Block Diagram of the Cyclone 5 FPGA Synthesizer with MIDI input, GUI and AC97 audio jacks
Terasic Cyclone 5 SOC PCB
The DE1-SoC Development Kit presents a robust hardware design platform built around the Altera System-on-Chip (SoC) FPGA, which combines the latest dual-core Cortex-A9 embedded cores with industry-leading programmable logic for ultimate design flexibility. Users can now leverage the power of tremendous re-configurability paired with a high-performance, low-power processor system. Altera’s SoC integrates an ARM-based hard processor system (HPS) consisting of processor, peripherals and memory interfaces tied seamlessly with the FPGA fabric using a high-bandwidth interconnect backbone. The DE1-SoC development board includes hardware such as high-speed DDR3 memory, video and audio capabilities, Ethernet networking, and much more.
The structure is almost the same as it used to be with some extensions:
- The ADSR module is now more complex and moved to a own section (ADSR behavior inspired by Chris Strellis FPGA Synth)
The next move is to speed up the design to run on 140 MHz, so 3 voices per Key can played the same time.
The Module requires 16 clock cycles to operate fully, because this is the longest path in the design including flipflops for registering and time for loading and saving to RAM registers. See the PLD Synth for a precise explanation of the function.
The complete ADSR processor has been joined with the loudness control of the channel and the tremolo function. Also the compressor section is put into this module. Calculation lengths of the DSP and the SYNTH modul do match for easier operation. Unlike the PLD synthesizer, this new version has a velocity curve included to be manipulated by the user one time.
Thanks to the following pages and authors: